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Here’s a VIM implementation of such a tracking receiver system. We use a dual channel 41 MHz A/D converter VME board feeding one of the FPDP inputs of the 6232 VIM-4 mezzanine module. The A/D also feeds the FPDP input of a 6099A digital delay board. With 512 MBytes of swinging buffer memory, the board can implement up to 1.5 seconds of delay at a sampling rate of 41 MHz. The delayed output feeds the second FPDP port of the 6232 receiver.

Inside the 6232, we can use the bypass path shown in red to route both channels of the raw A/D data right through the FPGA into the DSPs, where FFT’s are performed to detect energy.

Another strategy is to perform the FFT calculations right inside the FPGA, freeing up the DSPs for other tasks like demodulation and decoding.

Once energy is detected, the frequencies of interest are delivered as tuning commands from the DSPs to the digital receiver chips.

Up to 32 signals can be tracked simultaneously using the delayed signals from either of the two antennas.

Output data is delivered over the VMEbus or the optional RACE++ interface.

This whole 32-channel system occupies just 3 slots!

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